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参数资料
| 型号： | ICS9248YF-143LF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.37 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 11/16页 |
| 文件大小： | 506K |
| 代理商： | ICS9248YF-143LF-T |
4
ICS9248-143
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
t
i
B#
n
i
PD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B7
1
)
t
c
a
n
I
/
t
c
A
(
F
_
K
L
C
I
C
P
6
t
i
B8
11
)
t
c
a
n
I
/
t
c
A
(
6
K
L
C
I
C
P
5
t
i
B7
11
)
t
c
a
n
I
/
t
c
A
(
5
K
L
C
I
C
P
4
t
i
B3
11
)
t
c
a
n
I
/
t
c
A
(
4
K
L
C
I
C
P
3
t
i
B2
11
)
t
c
a
n
I
/
t
c
A
(
3
K
L
C
I
C
P
2
t
i
B1
11
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
I
C
P
1
t
i
B0
11
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
I
C
P
0
t
i
B8
1
)
t
c
a
n
I
/
t
c
A
(
0
K
L
C
I
C
P
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
t
i
B#
n
i
PD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B6
41
)
t
c
a
n
I
/
t
c
A
(
F
_
K
L
C
U
P
C
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B9
31
)
t
c
a
n
I
/
t
c
A
(
F
_
M
A
R
D
S
2
t
i
B2
41
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
U
P
C
1
t
i
B3
41
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
U
P
C
0
t
i
B5
41
)
t
c
a
n
I
/
t
c
A
(
0
K
L
C
U
P
C
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
t
i
B#
n
i
PD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B8
21
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
7
M
A
R
D
S
2
t
i
B9
21
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
M
A
R
D
S
1
t
i
B1
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
M
A
R
D
S
0
t
i
B2
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
M
A
R
D
S
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