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参数资料
| 型号： | ICS9248YF-179LF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 8/15页 |
| 文件大小： | 233K |
| 代理商： | ICS9248YF-179LF-T |
2
ICS9248-179
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Pin Configuration
PIN N UMBER
PIN NA ME
TY PE
DESCR IPTION
1, 11, 17, 21,
25, 36
VDD
PWR
3.3V Power supply for SD RAM output buffers, PCI output buffers,
reference output buffers and 48M H z output.
FS0
IN
Frequency select pin.
REF0
O UT
14.318 M H z reference clock.
FS1
IN
Frequency select pin.
REF1
O UT
14.318 M H z reference clock.
4, 5, 8, 14, 20, 24,
26, 34, 39, 42, 46
G ND
PWR
G round pin for outputs.
6
X 1
IN
Crystal input,nominally 14.318M Hz.
7
X 2
O UT
Crystal output, nominally 14.318M H z.
FS2
IN
Frequency select pin.
PCICLK_F
O UT
PCI clock output, not affected by PCI_STOP#.
FS3
IN
Frequency select pin.
PCICLK0
O UT
PCI clock output.
FS4
IN
Frequency select pin.
PCICLK1
O UT
PCI clock output.
16, 15, 13
PCICLK (4:2)
O UT
PCI clock outputs.
19, 18
AGPCLK (1:0)
O UT
A GP outputs defined as 2X PCI. These may not be stopped.
22
48M H z
O UT
48M Hz output clock.
AG PSEL
IN
A GP frequency select pin.
24_48M Hz
O UT
Clock output for super I/O/USB default is 24M Hz.
27
SCLK
IN
Clock pin of I
2C circuitry 5V tolerant.
28
SD ATA
I/O
Data pin for I
2C circuitry 5V tolerant.
29
AGP_STOP#
IN
Stops all AG P clocks besides the AG P_F clocks at logic 0 level,
when input low .
30
SD RA M _STO P#
IN
Stops all SD RAM clocks at logic 0 level, when input low .
31
PD#
IN
A synchronous active low input pin used to pow er down the device into a low
pow er state. The internal clocks are disabled and the V CO and the crystal are
stopped. The latency of the power dow n w ill not be greater than 3ms.
32
CPU_STO P#
IN
Stops all CPU CLKs clocks at logic 0 level, when input low
33
PCI_STO P#
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low .
35
SD RAM
O UT
SDRAM clock output.
37, 38, 43
NC
-
N o connect pins.
40, 44
CPUCLK (1:0)
O UT
CPU clock outputs.
41, 45, 48
V DD L
PWR
Supply for CPU and IOA PIC clocks at 2.5V nominal.
2
9
10
23
3
12
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9248YF-179-T | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-179-T | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-189-T | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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相关代理商/技术参数 |
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| ICS9248YF-189-T | 制造商:ICS 制造商全称:ICS 功能描述:AMD - K7⑩ Clock Generator for Mobile System |
| ICS9248YF-195LF-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM II/III & K6 |
| ICS9248YF-199-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for SIS 735/740 with AMD K7 Processor |
| ICS9248YF-39 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9248YF-64 | 制造商:ICS 制造商全称:ICS 功能描述:AMD-K7TM System Clock Chip |
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