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参数资料
| 型号： | ICS9248YF-195-T |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, MO-118, SSOP-48 |
| 文件页数： | 6/16页 |
| 文件大小： | 148K |
| 代理商： | ICS9248YF-195-T |
14
ICS9248-195
0375D—02/02/04
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-195. It is used to turn off the PCICLK clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-195 internally. The minimum that the PCICLK clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started
with a full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency
is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCICLK
PCI_STOP#
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| ICS9248YF-195-T | 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-39-T | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-66LF | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-72 | 200.01 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9248YF-199-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for SIS 735/740 with AMD K7 Processor |
| ICS9248YF-39 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9248YF-64 | 制造商:ICS 制造商全称:ICS 功能描述:AMD-K7TM System Clock Chip |
| ICS9248YF-65 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENDIUM II Systems |
| ICS9248YF-66 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
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