参数资料
型号: ICS9248YG-101LF-T
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 137 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: 6.10 MM, 0.50 MM PITCH, TSSOP-48
文件页数: 17/17页
文件大小: 352K
代理商: ICS9248YG-101LF-T
9
ICS9248-101
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-101. It is used to turn off the PCICLK [6:0] clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-101 internally. The minimum that the PCICLK [6:0] clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK [6:0] clocks. PCICLK [6:0] clocks are stopped in a low state and started with a full
high pulse width guaranteed. PCICLK [6:0] clock on latency cycles are only three rising PCICLK clocks, off latency is one
PCICLKclock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCICLK [6:0]
PCI_STOP#
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