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参数资料
| 型号： | ICS9250YF-08 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | SSOP-56 |
| 文件页数： | 13/15页 |
| 文件大小： | 239K |
| 代理商： | ICS9250YF-08 |
7
ICS9250-08
0378I—07/17/03
Shared Pin Operation -
Input/Output Pins
Fig. 1
The I/O pins designated by (input/output) on the ICS9250-
08 serve as dual signal functions to the device. During
initial power-up, they act as input pins. The logic level
(voltage) that is present on these pins at this time is read
and stored into a 4-bit internal data latch. At the end of
Power-On reset, (see AC characteristics for timing values),
the device changes the mode of operations for these pins
to an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins,
a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm(10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Figs. 1 and 2 show the recommended means of
implementing this function. In Fig. 1 either one of the
resistors is loaded onto the board (selective stuffing) to
configure the device’s internal logic. Figs. 2a and b
provide a single resistor loading option where either solder
spot tabs or a physical jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance
clock signals. The layouts have been optimized to provide
as little impedance transition to the clock signal as
possible, as it passes through the programming resistor
pad(s).
相关PDF资料 |
PDF描述 |
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| ICS9250YF-08LF | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS9250YF-08LF | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS9250YF-14-T | 149.69 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS9250YF-PPP-T | 149.69 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| ICS9250YF-16-T | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9250YF-09-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9250YF-10 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9250YF-11-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II/III Systems |
| ICS9250YF-12-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II/III Systems |
| ICS9250YF-13 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
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