参数资料
型号: ICS9250YF-23
元件分类: 时钟产生/分配
英文描述: 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: 0.300 INCH, MO-118, SSOP-56
文件页数: 15/15页
文件大小: 184K
代理商: ICS9250YF-23
9
ICS9250-23
0391B—09/18/03
Absolute Maximum Ratings
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Group Timing Relationship Table
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
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Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD + 0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
mA
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
mA
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
mA
Operating
IDD3.3V
Cl = 0 pF; Select @ 66M
119
280
Supply Current
IDDL2.5V
Cl = 0 pF; Select @ 66M
3
25
Power Down Current
IDD3.3VPD
Cl = 0 pF; With Input to Vdd or Gnd
600
mA
Input frequency
Fi
VDD = 3.3 V
14.318
MHz
Input Capacitance
1
CIN
Logic Inputs
5
pF
CINX
X1 & X2 pins
27
45
pF
Transition Time
1
TTrans
To 1st crossing of target Freq.
3
ms
Settling Time
1
TS
From 1st crossing to 1% target Freq.
1
3
ms
Clk Stabilization
1
TStab
From VDD = 3.3 V to 1% target Freq.
3
ms
TPZH,TPZL
output enable delay(all outputs)
1
10
ns
TPHZ,TPLZ
output disable delay(all outputs)
1
10
ns
1Guaranteed by design, not 100% tested in production.
mA
Delay
1
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