- 您现在的位置：买卖IC网 > PDF目录67706 > ICS93716YF-T (INTEGRATED DEVICE TECHNOLOGY INC) 93716 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 PDF资料下载
参数资料
| 型号： | ICS93716YF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 93716 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | MO-150, SSOP-28 |
| 文件页数： | 9/12页 |
| 文件大小： | 117K |
| 代理商： | ICS93716YF-T |
6
ICS93716
0420G—04/07/05
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were
the cycle (tc) decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, RL = 120, CL=15pF (unless otherwise
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
3
freqop
33
233
MHz
Application Frequency
Range
3
freqApp
60
170
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
100
s
Switching Characteristics
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, RL = 120 , CL=15pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
tPLH
1
CLK_IN to any output
5.5
ns
High-to low level propagation
delay time
tPHL
1
CLK_IN to any output
5.5
ns
Duty Cycle
DC
49
51
%
Input clock slew rate
tsl(I)
14
v/ns
Cycle to Cycle Jitter
1
tcyc-tcyc
100MHz < f < 170MHz
50
65
ps
Cycle to Cycle Jitter
1
tcyc-tcyc
f=66MHz
72
75
ps
Phase error
t(phase error)
4
-150
0
150
ps
Output to Output Skew
tskew
75
100
ps
Rise Time, Fall Time
tr, tf
See figure 8
550
950
ps
相关PDF资料 |
PDF描述 |
|---|---|
| ICS93V857YG-125LFT | 93V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| ICS93V857YG-130LFT | 93V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| ICS93V857YG-025T | 93V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| ICS93V857YG-125T | 93V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| ICS93V857YG-130T | 93V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS93716YG-T | 制造商:ICS 制造商全称:ICS 功能描述:Low Cost DDR Phase Lock Loop Clock Driver |
| ICS93718 | 制造商:ICS 制造商全称:ICS 功能描述:DDR and SDRAM Buffer |
| ICS93718CFLF | 功能描述:IC CLK BUFF 2:12 200MHZ 48-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:- 标准包装:1 系列:HiPerClockS™ 类型:扇出缓冲器（分配），多路复用器 电路数:1 比率 - 输入:输出:2:18 差分 - 输入:输出:是/无 输入:CML，LVCMOS，LVPECL，LVTTL，SSTL 输出:LVCMOS，LVTTL 频率 - 最大:250MHz 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:- 其它名称:800-1923-6 |
| ICS93718CFLFT | 功能描述:IC CLK BUFF 2:12 200MHZ 48-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:- 标准包装:1 系列:HiPerClockS™ 类型:扇出缓冲器（分配），多路复用器 电路数:1 比率 - 输入:输出:2:18 差分 - 输入:输出:是/无 输入:CML，LVCMOS，LVPECL，LVTTL，SSTL 输出:LVCMOS，LVTTL 频率 - 最大:250MHz 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:- 其它名称:800-1923-6 |
| ICS93718YFT | 制造商:ICS 制造商全称:ICS 功能描述:DDR and SDRAM Buffer |
发布紧急采购，3分钟左右您将得到回复。