参数资料
型号: ICS93722YFT
元件分类: 时钟及定时
英文描述: 93722 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
封装: 0.209 INCH, MO-150, SSOP-28
文件页数: 4/7页
文件大小: 83K
代理商: ICS93722YFT
4
ICS9372 2
0539F—04/12/05
Recommended Operating Conditions
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog / Core Supply Voltage
VDD, AVDD
2.3
2.5
2.7
V
VIL
VDD/2 - 0.5V
V
VIH
VDD/2 + 0.5V
V
Inpu Duty Cycle
IDC
40
60
Input max jitter
ITCYC
500
ps
Input Voltage Level
Timing Requirements
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Clock Frequency
1
freqop
66
200
MHz
Input Clock Duty Cycle
1
dtin
40
60
%
Clock Stabilization
1
tSTAB
from VDD = 2.5V to 1% target
frequency
100
s
1. Guaranteed by design, not 100% tested in production.
Switching Characteristics
TA = 0 - 70°C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
66 MHz
120
100 - 200 MHz
75
66 MHz
50
110
100 - 200 MHz
25
65
Phase Error
1
t(phase error)
CLK_INT to FB_INT
-150
50
150
ps
Output to output Skew
1
Tskew
VT = 50%
70
100
ps
Pulse Skew
1
Tskewp
100
ps
VT = 50%, 66 MHz to 100 MHz
49.5
50
50.5
VT = 50%, 101 MHz to 167 MHz
49
50
51
Single-ended 20 - 80 %
Load = 120 / 12 pF
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting output.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formula: duty cycle = twH / tC, where the cycle time (tC) decreases as the frequency increases.
Duty Cycle (differential)
1,3
950
ps
%
DC
Rise Time, Fall Time
1
tR, tF
450
550
Absolute Jitter
1
Tjabs
ps
Cycle to cycle Jitter
1,2
Tcyc-cyc
ps
相关PDF资料
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ICS93722YFLFT 93722 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
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