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参数资料
| 型号： | ICS94201DF-LF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, GREEN, SSOP-56 |
| 文件页数： | 15/20页 |
| 文件大小： | 358K |
| 代理商： | ICS94201DF-LF-T |
4
ICS94201
Preliminary Product Preview
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing
to byte 6.
2.
When writing to byte 14 - 15, byte 16 - 17 and byte 18 - 20, they must be written as a set. If for example, only byte 14
is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must
be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The
data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Notes:
R egister Name
Byte
D escription
Pw d Default
Functionality & Frequency Select
Register
0
Output frequency, hardware / I
2C frequency
select, spread spectrum & output enable
control register.
See individual byte
des cription
Output Control Registers
1-5
Active / inactive output control registers.
See individual byte
des cription
Byte Count Read Back Register
6
W riting to this register will configure byte
count and how many byte will be read back.
Do not write 00H to this byte.
06H
Latched Inputs Read Back
Register
7
The inverse of the latched inputs level could
be read back from this register.
See individual byte
des cription
W atchdog Control Registers
8 Bit[6:0]
W atchdog enable, watchdog status and
programm able ’safe’ frequency’ can be
configured in this register.
000,0000
VCO Control Selection Bit
8 Bit[7]
This bit select whether the output frequency
is control by hardware/byte 0 configurations
or byte 14&15 program ming.
0
W atchdog Timer Count Register
9
W riting to this register will configure the
number of seconds for the watchdog timer
to reset.
FFH
ICS Reserved Register
10
This is an unused register. W riting to this
register will not affect device functionality.
00H
Device ID, Vendor ID & Revision ID
Registers
11-12
Byte 11 bit[3:0] is ICS vendor id - 0001.
Other bits in these 2 registers designate
device revision ID of this part.
See individual byte
des cription
ICS Reserved Register
13
Don’t write into this register, writing 1’s will
cause malfunction.
00H
VCO Frequency Control Registers
14-15
These registers control the dividers ratio
into the phase detector and thus control the
VCO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
16-17
These registers control the spread
percentage am ount.
Depended on
hardware/byte 0
configuration
Output Dividers Control Registers
18-20
Changing bits in these registers result in
frequency divider ratio changes. Incorrect
configuration of group output divider ratio
can cause system m alfunction.
Depended on
hardware/byte 0
configuration
Group Skews Control Registers
21-23
Increm ent or decrement the group skew
amount as compared to the initial skew.
See individual byte
des cription
Output Rise/Fall Time Select
Registers
24
These register will control the group rise
and fall time.
See individual byte
des cription
Brief I
2C registers description for ICS94201
Programmable System Frequency Generator
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