参数资料
型号: ICS94201DFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 7/19页
文件大小: 0K
描述: IC FREQ GENERATOR PROGR 56-SSOP
标准包装: 1,000
类型: 时钟/频率发生器,多路复用器
PLL:
主要目的: Intel CPU 服务器
输入: 晶体
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:29
差分 - 输入:输出: 无/无
频率 - 最大: 500.03MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 56-BSSOP(0.295",7.50mm 宽)
供应商设备封装: 56-SSOP
包装: 带卷 (TR)
其它名称: 94201DFT
15
ICS94201
0428B - 11/28/05
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS94201
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a 5-
bit internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
mode the pins produce the specified buffered clocks to external
loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
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