参数资料
型号: ICS94209YFLF-T
元件分类: 时钟产生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: 0.300 INCH, SSOP-48
文件页数: 12/19页
文件大小: 217K
代理商: ICS94209YFLF-T
2
ICS94209
Third party brands and names are the property of their respective owners.
General Description
Pin Configuration
The ICS94209 is a single chip clock solution for desktop
designs using 630S chipsets. It provides all necessary clock
signals for such a system.
The ICS94209 belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I
2C interface as a vehicle for changing output
functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread
spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety
'Watchdog Timer' technology which will reset the frequency
to a safe setting if the system becomes unstable from over
clocking.
Power Groups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
E
D
O
M
1
2
n
i
P
7
2
n
i
P8
2
n
i
P0
3
n
i
P1
3
n
i
P
01
1
M
A
R
D
S0
1
M
A
R
D
S9
M
A
R
D
S8
M
A
R
D
S
1#
P
O
T
S
_
U
P
C#
P
O
T
S
_
I
C
P#
P
O
T
S
_
M
A
R
D
S#
D
P
MODE Pin Power Management Control Input
PIN NU MB ER
PIN N A ME
TY PE
D ESCR IPTION
1, 7, 15, 22, 25,
35, 43
VDD
P WR
3.3V P ow er supply for SD RA M output buffers, PCI output buffers,
reference output buffers and 48M H z output
A G P S EL
IN
A G P frequency select pin.
REF0
O U T
14.318 M H z reference clock.
F S3
IN
F requency select pin.
REF1
O U T
14.318 M H z reference clock.
4, 14, 18, 19, 29,
32, 39, 44
G N D
P WR
G round pin for 3V outputs.
5
X 1
IN
C rystal input,nominally 14.318M H z.
6
X 2
O U T
C rystal output, nominally 14.318M H z.
F S1
IN
F requency select pin.
PCIC LK _F
O U T
P CI clock output, not affected by P CI_STO P #
F S2
IN
F requency select pin.
PCIC LK 0
O U T
P CI clock output.
13, 12, 11, 10
PCICLK (4:1)
O U T
P CI clock outputs.
17, 16,
A G P (1:0)
O U T
A G P outputs defined as 2X PC I. These may not be stopped.
F S0
IN
F requency select pin.
48M H z
O U T
48M H z output clock
MO D E
IN
P in 27, 28, 30, & 31 function select pin
0=D esktop 1=M obile mode
24_48M H z
O U T
C lock output for super I/O /U S B default is 24M H z
23
SDATA
I/O
Data pin for I
2
C circuitry 5V tolerant
24
S CLK
IN
C lock pin of I
2
C circuitry 5V tolerant
CP U_STOP#
IN
S tops all PCICLK s besides the PCICLK _F clocks at logic 0 level, w hen input
is low and M O D E pin is in M obile mode
SD RA M 11
O U T
S D RA M clock output
PCI_STO P #
IN
S tops all CPU CLK s clocks at logic 0 level, w hen input is low and M O D E pin
is in M obile mode
SD RA M 10
O U T
S D RA M clock output
S D R A M 9
O U T
S D RA M clock output
SDRA M _STOP#
IN
S tops all SD RA M clocks at logic 0 level, w hen input is low and M O D E pin
is in M obile mode
PD #
IN
A synchronous active low input pin used to pow er dow n the device into a low
pow er state. The internal clocks are disabled and the V CO and the crystal are
stopped. The latency of the pow er dow n w ill not be greater than 3ms.
S D R A M 8
O U T
S D RA M clock output
26 33, 34, 36, 37,
38, 40, 41, 42
SD RA M (12, 7:0)
O U T
S D RA M clock outputs
45, 46, 47
CP U C LK (2:0)
O U T
C PU clock outputs.
48
V D D L
P WR
P ow er pin for the CP U CLK s. 2.5V
31
20
2
8
9
21
3
30
27
28
相关PDF资料
PDF描述
ICS94210YF-PPP-T-LF 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS94210YF-PPP-T-LF 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS94210YF-T 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS94210YFLF-T 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS94220YFLF-T 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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