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参数资料
| 型号： | ICS950201YFLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, LEAD FREE, MO-118, SSOP-56 |
| 文件页数： | 5/16页 |
| 文件大小： | 224K |
| 代理商： | ICS950201YFLF-T |
13
Integrated
Circuit
Systems, Inc.
ICS950201
0460I—12/13/04
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2C configuration to be stoppable via assertion
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state
of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The
CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
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| ICS950211BF | 功能描述:IC TIMING CTRL HUB P4 56-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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