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参数资料
| 型号： | ICS950208YFLFT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, MO-118, SSOP-48 |
| 文件页数： | 13/19页 |
| 文件大小： | 133K |
| 代理商： | ICS950208YFLFT |
3
Integrated
Circuit
Systems, Inc.
ICS950208
0464B—08/04/03
Pin Description (Continued)
PIN PIN
PIN
#
NAME
TYPE
25
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
26
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
27
3V66_3
OUT 3.3V 66.66MHz clock output
28
3V66_2
OUT 3.3V 66.66MHz clock output
29
GND
PWR Ground pin.
30
3V66_1
OUT 3.3V 66.66MHz clock output
31
3V66_0
OUT 3.3V 66.66MHz clock output
32
VDD3V66
PWR Power pin for the 3V66 clocks.
33
GND
PWR Ground pin.
34
AVDD
PWR 3.3V Analog Power pin for Core PLL
35
IREF
OUT
This pin establishes the reference current for the differential current-mode output pairs. This
pin requires a fixed precision resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
36
GNDCPU
PWR Ground pin for the CPU outputs
37
CPUCLKC1
OUT
"Complimentary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
38
CPUCLKT1
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
39
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
40
CPUCLKC0
OUT
"Complimentary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
41
CPUCLKT0
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
42
PD#
IN
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the
power down will not be greater than 1.8ms.
43
GNDCPU
PWR Ground pin for the CPU outputs
44
CPUCLKC2
OUT
"Complimentary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
45
CPUCLKT2
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
46
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
47
GNDREF
PWR Ground pin for the REF outputs.
48
REF0/MULTSEL0*
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference
clock.
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
DESCRIPTION
~ This output has 2X drive
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| ICS950211 | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for P4 |
| ICS950211BF | 功能描述:IC TIMING CTRL HUB P4 56-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS950211BFLF | 功能描述:IC TIMING CTRL HUB P4 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS950211BFLFT | 功能描述:IC TIMING CTRL HUB P4 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS950211BFT | 功能描述:IC TIMING CTRL HUB P4 56-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:TCH™ 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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