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参数资料
| 型号： | ICS951702YGLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 146.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56 |
| 文件页数： | 5/12页 |
| 文件大小： | 159K |
| 代理商： | ICS951702YGLF-T |
2
ICS951702
Advance Information
0664—07/29/02
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Internal pull-down resistor of 120K to GND on indicated inputs.
3:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 36, 43, 48, 56
VDDL
PWR
Power supply pins, nominal 2.5V
2
IOAPIC
OUT
2.5V clock outputs
3, 11, 16, 21,
29, 37, 42, 49,
52
GND
PWR
Ground pins
4
X1
IN
Crystal input,nominally 14.318MHz.
5
X2
OUT
Crystal output, nominally 14.318MHz.
6
AVDD
PWR
Analog power supply for 3.3V
FS0
2, 3
IN
Frequency select pin.
REF0
OUT
14.318 MHz reference clock.
8, 17, 22, 27
VDD
PWR
Power supply pins, nominal 3.3V
FS1
2, 3
IN
Frequency select pin.
AGP0
OUT
AGP outputs defined as 2X PCI.
10
AGP1
OUT
AGP output defined as 2X PCI.
PCICLK_F
OUT
Free running PCI clock
FS2
1, 2
IN
Frequency select pin.
20, 19, 18, 15,
14, 13
PCICLK (5:0)
OUT
PCI clock outputs.
23
PCICLK6
OUT
PCI clock output (selectable 1X or 2X via I
2C)
24
PCI_STOP#
IN
Stops all PCICLKs at logic 0 level, when input low besides the
PCICLK_F clocks which are controllable by I
2C bits whether they are
free running or stopped by PCI_STOP.
25
CPU_STOP#
IN
Stops all CPUCLKs at logic 0 level, when input low. The individual
CPU clocks are controllable by I
2C bits whether they are free
running or stopped by CPU_STOP.
PD#
IN
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms.
Vtt_PWRGD
IN
This pin acts as a dual function input pin for Vtt_PWRGD and PD#
signal. When Vtt_PWRGD goes high the frequency select will be
latched at power on thereafter the pin is an asynchronous active low
power down pin.
FS3
2, 3
IN
Frequency select pin
48MHz
OUT
48MHz output clock
30
SDATA
I/O
Data pin for I
2C circuitry 5V tolerant
31
SCLK
IN
Clock pin of I
2C circuitry 5V tolerant
33, 35, 39, 41,
45, 47, 51
DDRT (6:0)
OUT
"True" clocks of differential pair DDR SDRAM outputs - 2.5V
32, 34, 38, 40,
44, 46, 50
DDRC (6:0)
OUT
"Complementry" clocks of differential pair
DDR SDRAM outputs - 2.5V
53, 54
CPUCLK (1:0)
OUT
2.5V CPU clocks
55
CPUCLK_F
OUT
Free running CPU clock. Not affected by the CPU_STOP#.
9
7
12
28
26
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