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参数资料
| 型号： | ICS952001YGLFT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | TSSOP-48 |
| 文件页数： | 7/17页 |
| 文件大小： | 212K |
| 代理商： | ICS952001YGLFT |
15
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
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相关代理商/技术参数 |
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| ICS952003 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Programmable Timing Control Hub? for P4? processor |
| ICS952003YFT | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub for P4⑩ processor |
| ICS952004 | 制造商:ICS 制造商全称:ICS 功能描述:Programmable Timing Control Hub⑩ for P4⑩ processor |
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