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参数资料
| 型号： | ICS952606YFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | LEAD FREE, MO-118, SSOP-48 |
| 文件页数： | 6/20页 |
| 文件大小： | 162K |
| 代理商： | ICS952606YFLFT |
14
Integrated
Circuit
Systems, Inc.
ICS952606
0717F—06/10/05
I
2C Table: Byte Count Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
BC7
RW
-
0
Bit 6
BC6
RW
-
0
Bit 5
BC5
RW
-
0
Bit 4
BC4
RW
-
0
Bit 3
BC3
RW
-
1
Bit 2
BC2
RW
-
0
Bit 1
BC1
RW
-
0
Bit 0
BC0
RW
-
0
I
2C Table: Reserved
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RESERVED
-
X
Bit 6
RESERVED
-
X
Bit 5
RESERVED
-
X
Bit 4
RESERVED
-
X
Bit 3
RESERVED
-
X
Bit 2
RESERVED
-
X
Bit 1
RESERVED
-
X
Bit 0
RESERVED
-
X
I
2C Table: Reserved
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
M/N prog Enable
-
Disable
Enable
0
Bit 6
RESERVED
-
X
Bit 5
RESERVED
-
X
Bit 4
RESERVED
-
X
Bit 3
RESERVED
-
X
Bit 2
RESERVED
-
X
Bit 1
RESERVED
-
X
Bit 0
RESERVED
-
X
I
2C Table: VCO Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
N Div8
N Divider Bit 8
RW
-
X
Bit 6
M Div6
RW
-
X
Bit 5
M Div5
RW
-
X
Bit 4
M Div4
RW
-
X
Bit 3
M Div3
RW
-
X
Bit 2
M Div2
RW
-
X
Bit 1
M Div1
RW
-
X
Bit 0
M Div0
RW
-
X
RESERVED
Byte 10
-
RESERVED
-
RESERVED
The decimal
representation of M Div
(6:0) is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
-
Byte 8
-
Byte 11
-
Byte 9
-
Writing to this register
will configure how
many bytes will be read
back, default is 08 = 8
bytes.
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