参数资料
型号: ICS952623
英文描述: Programmable Timing Control Hub for Next Gen P4 processor
中文描述: 可编程定时控制中心,为下一代P4处理器
文件页数: 14/27页
文件大小: 329K
代理商: ICS952623
14
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
I
2
C Table: Overclocking Output Control Register
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
-
Name
Reserved
Reserved
Reserved
Reserved
Control Function
Reserved
Reserved
Reserved
Reserved
1: over-clk
0: normal mode
Over Clocking
Over Clocking
Reserved
Type
RW
RW
RW
RW
0
-
-
-
-
1
-
-
-
-
PWD
0
0
0
0
Bit 3
Over Clocking
R
0
Bit 2
Bit 1
Bit 0
Over Clocking
Over Clocking
Reserved
R
R
0
0
0
RW
-
-
I
2
C Table: VCO Control Select Bit Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Programming ENABLE
Enables prograaming
bytes 11-14
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RW
DISABLED
ENABLED
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
Bit 0
RESERVED
RESERVED
RW
-
-
0
I
2
C Table: VCO Frequency Control Register
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Name
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Control Function
N Divider Bit 8
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
-
Byte 10
-
-
-
-
-
-
-
The decimal
representation of M
Div (6:0) is equal to
reference divider
value. Default at
power up = latch-in or
Byte 0 Rom table.
-
-
-
-
-
Byte 11
-
-
-
-
Byte 9
See over clocking per bit 1
and 2
00= +15%, 01 = +20%
10= +5%, 11= +10%
-
-
-
-
-
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