参数资料
型号: ICS952623YFT
英文描述: Programmable Timing Control Hub for Next Gen P4 processor
中文描述: 可编程定时控制中心,为下一代P4处理器
文件页数: 16/27页
文件大小: 329K
代理商: ICS952623YFT
16
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to
be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the
PCI_STOP register bit.
PCI Stop Functionality
#
P
O
T
S
_
C
P
U
P
C
#
U
P
C
C
R
S
#
C
R
S
6
6
V
3
I
C
P
/
C
P
T
O
D
/
B
S
U
F
E
R
e
o
N
1
l
m
r
N
l
m
r
N
l
m
r
N
l
m
r
N
z
H
M
6
6
z
H
M
3
3
z
H
M
8
4
z
H
M
8
1
3
1
0
l
m
r
N
l
m
r
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6
*
f
r
t
o
w
o
L
z
H
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6
6
w
o
L
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8
4
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8
1
3
1
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all
PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,
the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and
the SRC# will latch low as shown below.
PCI_STOP#
Tsu
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# Assertion (transition from '1' to '0')
The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After
detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free
manner.
PCI_STOP#
Tsu
Tdrive_SRC
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - De-assertion
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