参数资料
型号: ICS952623YGT
英文描述: Programmable Timing Control Hub for Next Gen P4 processor
中文描述: 可编程定时控制中心,为下一代P4处理器
文件页数: 17/27页
文件大小: 329K
代理商: ICS952623YGT
17
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU_STOP# Functionality
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Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the I2C
CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a '0', CPU output will stop CPU_True
= HIGH and CPU_Complement = LOW. When the I2C CPU_Stop tri-state bit corresponding to the CPU output of interest is
programmed to a '1', CPU outputs will be tri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - Assertion (transition from '1' to '0')
With the de-assertion of CPU_Stop# all stopped CPU outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 CPU clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped CPU outputs will be driven High within 10nS of CPU_Stop# de-assertion to
a voltage greater than 200mV.
CPU_Stop#
Tdrive_CPU_Stop, 10nS >200mV
CPU
CPU#
CPU Internal
CPU_STOP# - De-assertion (transition from '0' to '1')
相关PDF资料
PDF描述
ICS952623 Programmable Timing Control Hub for Next Gen P4 processor
ICS952623YFT Programmable Timing Control Hub for Next Gen P4 processor
ICS952623YGT Programmable Timing Control Hub for Next Gen P4 processor
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