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| 型号： | ICS952703YFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 217.9 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | LEAD FREE, MO-118, SSOP-48 |
| 文件页数： | 7/17页 |
| 文件大小： | 143K |
| 代理商： | ICS952703YFLFT |
15
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
0813B—05/17/05
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next
high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2C configuration to be stoppable via assertion
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state
of the stopped CPU signals is CPUT=Low and CPUC=High.There is to be no change to the output drive current values.The CPUT
will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#
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CPU_STOP#
CPUT
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| ICS952801CFLF | 功能描述:IC TIMING CTRL HUB K8 48-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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