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参数资料
| 型号： | ICS954101YGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.240 INCH, 0.020 INCH PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件页数： | 11/17页 |
| 文件大小： | 189K |
| 代理商： | ICS954101YGLFT |
3
Integrated
Circuit
Systems, Inc.
ICS954101
0815F—08/15/05
Pin Description (Continued)
Pin #
PIN NAME
TYPE
DESCRIPTION
29
GND
PWR
Ground pin.
30
SRCCLKC5
OUT
Complement clock of differential SRC clock pair.
31
SRCCLKT5
OUT
True clock of differential SRC clock pair.
32
SRCCLKC6
OUT
Complement clock of differential SRC clock pair.
33
SRCCLKT6
OUT
True clock of differential SRC clock pair.
34
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
35
CPUCLKC2_ITP/SRCCLKC_7
OUT
Complimentary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
36
CPUCLKT2_ITP/SRCCLKT_7
OUT
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These
are current mode outputs. External resistors are required for voltage bias.
Selected by ITP_EN input.
37
VDDA
PWR
3.3V power for the PLL core.
38
GNDA
PWR
Ground pin for the PLL core.
39
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
40
CPUCLKC1
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
42
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
43
CPUCLKC0
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
45
GND
PWR
Ground pin.
46
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
47
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
48
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
49
X2
OUT
Crystal output, Nominally 14.318MHz
50
X1
IN
Crystal input, Nominally 14.318MHz.
51
GND
PWR
Ground pin.
52
REFOUT
OUT
Reference Clock output
53
FS_C/TEST_SEL
IN
3.3V tolerant input for CPU frequency selection. Low voltage threshold
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
54
PCICLK0
OUT
PCI clock output.
55
PCICLK1
OUT
PCI clock output.
56
PCICLK2
OUT
PCI clock output.
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