- 您现在的位置：买卖IC网 > PDF目录79612 > ICS95V857CLLF-T (INTEGRATED DEVICE TECHNOLOGY INC) 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 PDF资料下载
参数资料
| 型号： | ICS95V857CLLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 4.40 MM, 0.40 MM PITCH, ROHS COMPLIANT, MO-153, TVSOP-48 |
| 文件页数： | 10/13页 |
| 文件大小： | 136K |
| 代理商： | ICS95V857CLLF-T |
6
ICS95V857C
1190A—12/16/05
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
2.5V+0.2V @ 25
oC
45
233
MHz
Application Frequency
Range
freqApp
2.5V+0.2V @ 25
oC
95
220
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
15
s
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
tPLH
1
CLK_IN to any output
3.5
ns
High-to low level propagation
delay time
tPLL
1
CLK_IN to any output
3.5
ns
Output enable time
tEN
PD# to any output
3
ns
Output disable time
tdis
PD# to any output
3
ns
Period jitter
Tjit (per)
100MHz to 200MHz
-30
30
ps
Half-period jitter
t(jit_hper)
100MHz to 200MHz
-75
75
ps
Input clock slew rate
tsl(i)
14
V/ns
Output clock slew rate
tsl(o)
12
V/ns
Cycle to Cycle Jitter
1
Tcyc-Tcyc
100MHz to 200MHz
-50
50
ps
Static Phase Offset
t(static phase offset)
4
-50
0
50
ps
Output to Output Skew
Tskew
40
ps
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9112AG-27 | 9112 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS95V2F857ALT | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| ICS95V157AGI | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| ICS95V2F857AGT | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| ICS95V857AGI-T | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS95V860 | 制造商:ICS 制造商全称:ICS 功能描述:2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) |
| ICS95V860YHLF-T | 制造商:ICS 制造商全称:ICS 功能描述:2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) |
| ICS95VLP857AGLF | 功能描述:IC CLOCK DRIVER 2.5V 48-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS95VLP857AGLFT | 功能描述:IC CLOCK DRIVER 2.5V 48-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ICS95VLP857AGLF-T | 制造商:INTEGRATED DEVICE TECHNOLOGY 功能描述: |
发布紧急采购，3分钟左右您将得到回复。