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参数资料
| 型号： | ICS98UAE877AKLFIT |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER |
| 中文描述： | 1.5V的低功耗，宽范围频率时钟驱动器 |
| 文件页数： | 8/18页 |
| 文件大小： | 275K |
| 代理商： | ICS98UAE877AKLFIT |
ICS98UAE877A
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
8
ICS98UAE877A
7181/2
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, Industrial: T
A
= -40°C to +85°C; Supply Voltage AV
DD
/V
DDQ
= 1.5V ± 0.075V.
Parameter
1
freq
OP
Max Clock Frequency
2
1.5V ± 0.075V @ 25
°
C
freq
APP
Application Frequency Range
3
1.5V ± 0.075V @ 25
°
C
d
TIN
Input Clock Duty Cycle
T
STAB
CLK Stabilization
4
Symbol
1
2
not required to meet the other timing parameters. (Used for low speed system debug.)
3
Application clock frequency indicates a range over which the PLL must meet all timing parameters.
4
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (
t
), after power-up.
During normal operation, the stabilization time is also the time required for the integrated PLL circuit to ob-
tain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic low state,
enter the power-down mode and later return to active operation. CLK and CLK may be left floating after
they have been driven low for one complete clock cycle.
The PLL must be able to handle spread spectrum induced skew.
Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is
Conditions
Min.
95
160
40
Max.
410
410
60
9
Units
MHz
MHz
%
μ
s
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