参数资料
型号: ICS9DB306BFLFT
元件分类: 时钟及定时
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封装: 5.30 X 10.20 MM, 1.75 MM HEIGHT, MO-150, SSOP-28
文件页数: 14/16页
文件大小: 268K
代理商: ICS9DB306BFLFT
9DB306BL
www.icst.com/products/hiperclocks.html
REV. B JUNE 16, 2006
7
Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin.The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS9DB306 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
CC and VCCA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required.
Figure 1 illus-
trates how a 24
resistor along with a 10F and a .01F by-
pass capacitor should be connected to each V
CCA pin.
FIGURE 1. POWER SUPPLY FILTERING
24
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VCC
相关PDF资料
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ICS9DB306BF 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
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