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参数资料
| 型号： | ICS9DB801CGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | Eight Output Differential Buffer for PCI Express (50-200MHz) |
| 中文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件页数： | 7/19页 |
| 文件大小： | 215K |
| 代理商： | ICS9DB801CGLFT |
IDT
TM
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz)
ICS9DB801C REV C 08/16/07
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
7
Symbol
VDD_A
VDD_In
V
IL
V
IH
Ts
Tambient
Tcase
Parameter
Min
Max
4.6
4.6
Units
V
V
V
V
°
C
°C
°C
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
GND-0.5
V
DD
+0.5V
150
70
115
-65
0
ESD prot
2000
V
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input High Current
I
IH
V
IN
= 0 V; Inputs with no pull-up
MIN
2
TYP
MAX
V
DD
+ 0.3
0.8
5
UNITS NOTES
V
V
uA
3.3 V +/-5%
3.3 V +/-5%
V
IN
= V
DD
GND
- 0.3
-5
I
IL1
resistors
-5
uA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200
uA
I
DD3.3PLL
I
DD3.3ByPass
175
160
50
1
200
175
70
4
200
mA
mA
mA
mA
MHz
all diff pairs driven
all differential pairs tri-stated
PLL Mode
Bypass Mode (Revision B/REV
ID = 1H)
Bypass Mode (Revision C/REV
ID = 2H)
Input Frequency
F
iPLL
50
Input Frequency
F
iBypass
0
333.33
MHz
Input Frequency
F
iBypass
0
400
MHz
Pin Inductance
1
L
pin
C
IN
C
OUT
7
4
4
nH
pF
pF
1
1
1
Logic Inputs
Output pin capacitance
PLL Bandwidth when
PLL_BW=0
PLL Bandwidth when
PLL_BW=1
From V
DD
Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
Triangular Modulation
DIF output enable after
SRC_Stop# de-assertion
DIF output enable after
PD# de-assertion
Fall time of PD# and
SRC_STOP#
Rise time of PD# and
SRC_STOP#
1.5
2.4
3
3.4
MHz
1
0.7
1
1.4
MHz
1
Clk Stabilization
1,2
T
STAB
0.5
1
ms
1,2
Modulation Frequency
fMOD
30
33
kHz
1
Tdrive_SRC_STOP#
10
15
ns
1,3
Tdrive_PD#
300
us
1,3
Tfall
5
ns
1
Trise
5
ns
2
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Time from deassertion until outputs are >200 mV
I
DD3.3PD
Input Capacitance
1
Input Low Current
Powerdown Current
PLL Bandwidth
BW
Full Active, C
L
= Full load;
Operating Supply Current
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| ICS9DB803DFLF | 功能描述:IC BUFFER 8OUTPUT DIFF 48-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:PCI Express® (PCIe) 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
| ICS9DB803DFLFT | 功能描述:IC BUFFER 8OUTPUT DIFF 48-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:PCI Express® (PCIe) 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
| ICS9DB803DGILF | 功能描述:IC BUFFER 8OUTPUT DIFF 48-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:PCI Express® (PCIe) 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
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