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参数资料
| 型号： | ICSLV218RILFT |
| 元件分类： | 时钟及定时 |
| 英文描述： | 218 SERIES, LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, MO-153, SSOP-28 |
| 文件页数： | 2/6页 |
| 文件大小： | 141K |
| 代理商： | ICSLV218RILFT |
Dual 1-to-8 Low Voltage Clock Buffer/Translator
MDS LV218 A
2
Revision 083105
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV218
PRELIMINARY INFORMATION
Pin Assignment
Suggested Layout
Pin Descriptions
18
7
17
8
16
9
15
QA3
10
QA4
11
GND
12
QB4
13
GND
14
QA5
GND
QB5
QA6
QB6
VDD
QA7
QB7
22
21
20
19
OE
QB3
5
6
VDDA
VDDB
24
23
VDDB
3
4
QA1
QA2
QB2
26
25
QB1
1
2
INA
QA0
QB0
28
27
INB
A
G
B
G
V
G
0.01 F
NOTE: 33 ohm series termination resistors for each output are
essential for operation.
For simplicity, series termination resistors are not shown for
the outputs, but should be placed as close to the device as
possible. It is most critical to have the 0.01 F decoupling
capacitors closest.
A
V
B
G
= connect to VDDA
= connect to VDD
= connect to VDDB
= connect to low
inductance ground plane
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
INA
Input
Clock input for eight A outputs. 3.3 V tolerant.
2, 3, 4
QA0, QA1, QA2
Output
Clock A outputs.
5, 6
VDDA
Power
Power supply for QA outputs. Connect to a voltage from 2.5 V to 3.3 V.
7, 8
QA3, QA4
Output
Clock A outputs.
9, 10
GND
Power
Connect to ground.
11, 12, 13 QA5, QA6, QA7
Output
Clock A outputs.
14
OE
Input
Output Enable. Tri-states all clock outputs when this input is low. Internal pull-up to VDDIN.
15
VDD
Power
Power supply for inputs. Connect to 2.5 V.
16, 17, 18 QB7, QB6, QB5
Output
Clock B outputs.
19, 20
GND
Power
Connect to ground.
21, 22
QB4, QB3
Output
Clock B outputs.
23, 24
VDDB
Power
Power supply for QB outputs. Connect to a voltage from 1.8 V to 2.5 V.
25, 26, 27 QB2, QB1, QB0
Output
Clock B outputs.
28
INB
Input
Clock input for eight B outputs. 3.3 V tolerant.
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