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参数资料
| 型号： | ICSLV218RILFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 218 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, MO-153, SSOP-28 |
| 文件页数： | 5/7页 |
| 文件大小： | 188K |
| 代理商： | ICSLV218RILFT |
ICSLV218
DUAL 1 TO 8 LOW VOLTAGE CLOCK BUFFER/TRANSLATOR
FAN OUT BUFFER
IDT / ICS DUAL 1 TO 8 LOW VOLTAGE CLOCK BUFFER/TRANSLATOR 5
ICSLV218
REV A 083105
AC Electrical Characteristics
Unless stated otherwise, VDDIN = VDDA = VDDB = 2.5 V ±10%, Ambient Temperature = -40 to 85°C
Notes:
1. Between any two A outputs, or any two B outputs, with equal loading.
2. Between any clock A output and any clock B output with INA connected to INB, and equal loading.
3. Care must be taken not to exceed the absolute maximum junction temperature or power dissipation rating of the package:
Power dissipated = (16 outputs x frequency x VDD2 x CL) < [(Tj - Ta) / θJA].
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Clock Frequency
FIN
INA or INB, Note 3
0
200
MHz
Propagation Delay, INA to
QA0-QA7
CL = 10 pF
5
ns
Propagation Delay, INB to
QB0-QB7
CL = 10 pF
5
ns
Output Clock Rise Time
20% to 80%, CL=10 pF
2.5
ns
Output Clock Fall Time
80% to 20%, CL=10 pF
2.5
ns
Output Duty Cycle
CL=10 pF
45
48
55
%
Output to Output Skew
Measured on rising
edge at VDD/2, Note 1
100
150
ps
Output Clock A to B Skew
At VDD/2, Note 2
1500
ps
Output Enable Time
OE high to output on
20
ns
Output Disable Time
OE low to tri-state
20
ns
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
θ
JA
Still air
100
°C/W
θ
JA
1 m/s air flow
80
°C/W
θ
JA
3 m/s air flow
67
°C/W
Thermal Resistance Junction to Case
θ
JC
60
°C/W
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