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参数资料
| 型号： | ICSLV810SI |
| 元件分类： | 时钟及定时 |
| 英文描述： | 810 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 12/13页 |
| 文件大小： | 241K |
| 代理商： | ICSLV810SI |
Buffer/Clock Driver
MDS LV810 D
8
Revision 062105
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSLV810
AC Electrical Characteristics—Bank C
VDDC = 2.5 V, Ambient Temperature -40
° C to +85° C, unless otherwise noted
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Skew between outputs of same
package
CL = 3 pF,
RL = 500
-200
200
ps
Skew between opposite
transitions of same output
CL = 3 pF,
RL = 500
-200
200
ps
Propagation Delay
tpLH/tpHL
CL = 3 pF,
RL = 500
,
VDDC = 1.5 V
5.5
ns
CL = 3 pF,
RL = 500
,
VDDC = 2.5 V
1.5
2.6
3.5
ns
Part to Part Skew
CL = 3 pF,
RL = 500
VDDC = 1.5 V
-1
1
ns
CL = 3 pF,
RL = 500
VDDC = 2.5 V
-650
650
ps
Output Rise Time
20% to 80%
tr(o)
CL = 3 pF,
RL = 500
VDDC = 1.5 V
1.0
ns
CL = 3 pF,
RL = 500
VDDC = 2.5 V
0.8
ns
Output Fall Time
80% to 20%
tf(o)
CL = 3 pF,
RL = 500
VDDC = 1.5 V
1.0
ns
CL = 3 pF,
RL = 500
VDDC = 2.5 V
0.8
ns
Peak-to-Peak Jitter
tJP
All Outputs,
VDDC = 1.5 V
34
ps
All Outputs,
VDDC = 2.5 V
50
ps
Duty Cycle
Measured at VDD/2
DC
CL = 3 pF,
RL = 500
45
55
%
Output Frequency Range
1
170
MHz
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