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参数资料
| 型号： | ICSSSTU32864 |
| 英文描述： | 25-Bit Configurable Registered Buffer |
| 中文描述： | 25位可配置注册缓冲区 |
| 文件页数： | 8/11页 |
| 文件大小： | 110K |
| 代理商： | ICSSSTU32864 |
8
ICSSSTU32864
0727C—04/15/04
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
300
f
clock
Clock frequency
MHz
ns
ns
ns
ns
0.75
0.9
0.50
0.70
Hold time, fast slew rate
2, 4
Hold time, slow slew rate
3, 4
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
V
DD
= 1.8V ±0.1V
UNITS
PARAMETERS
Data before CLK
↑
, CLK#
↓
Data after CLK
↑
, CLK#
↓
Setup time
SYMBOL
t
S
T
h
Notes:
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
From
(Input)
(Output)
MIN
270
1.41
TYP
MAX
fmax
t
PDM1
t
PDMSS2
t
phl
Notes: 1. Includes 350ps test-load transmission-line delay
2. Guaranteed by design, not 100% tested in production.
MHz
ns
CLK, CLK#
CLK, CLK#
RESET#
Q
Q
Q
1.85
3
ns
SYMBOL
V
DD
= 1.8V ±0.1V
UNITS
To
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
V
DD
= 1.8V ± 0.1V
MIN
1
1
MAX
4
4
1
dV/dt_r
dV/dt_f
dV/dt_
1
V/ns
V/ns
V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
UNIT
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相关代理商/技术参数 |
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|---|---|
| ICSSSTUA32S869B | 制造商:ICS 制造商全称:ICS 功能描述:14-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUAF32865A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32865AHLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866B | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866BHLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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