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参数资料
| 型号： | ICSSSTUAF32866BHLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 通用总线功能 |
| 英文描述： | 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | SSSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封装： | LEAD FREE, MO-205CC, BGA-96 |
| 文件页数： | 17/31页 |
| 文件大小： | 563K |
| 代理商： | ICSSSTUAF32866BHLFT |
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IDT74SSTUBF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
17
IDT74SSTUBF32866B
7067/9
CONFIDENTIAL
Register Timing
Timing Diagram for SSTUBF32866B Used as a Single Device; C0 = 0, C1 = 0, RESET Switches from L to H
NOTES:
1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held low for a minimum time of t
ACTMAX
, to avoid false
error.
2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse.
n
n +1
n + 2
n + 3
n + 4
t
PDM,
t
PDMSS
CLK to Q
t
SU
CLK
CLK
D1 - D25
PARIN
QERR
Data to QERR Latency
CLK to QERR
t
PHL,
t
PLH
Q1 - Q25
t
SU
t
H
t
H
CSR
DCS
RESET
H, L, or X
H or L
(1)
t
ACT
(1)
PPO
CLK to PPO
t
PD
(2)
CLK to QERR
t
PHL
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| ICSSSTUAF32866C | 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866CHLFT | 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTUAF32866C | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866CHLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868AHLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32868B | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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