- 您现在的位置：买卖IC网 > PDF目录67710 > ICSSSTUF32864AYHLF-T SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 PDF资料下载
参数资料
| 型号： | ICSSSTUF32864AYHLF-T |
| 元件分类： | 锁存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封装： | MO-205CC, LFBGA-96 |
| 文件页数： | 10/11页 |
| 文件大小： | 111K |
| 代理商： | ICSSSTUF32864AYHLF-T |
8
ICSSSTUF32864A
0987B—09/28/04
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
MIN
MAX
UNITS
fclock
Clock frequency
335
MHz
tW
1ns
tACT
10
ns
tINACT
15
ns
Setup time
DCS before CK, CK
↓,
CSR high; CSR before
CK, CK
↓, DCS high
0.7
ns
DCS before CK, CK
↓,
CSR Low
0.5
ns
DODT, DCKE and data
before CK, CK
↓
0.5
ns
Setup time
PAR_IN before CK, CK
↓
ns
DCS, DODT, DCKE and
data after CK, CK
↓
0.50
ns
PAR_IN after CK, CK
↓
0.50
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
tSU
th
Notes:
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
Setup time
Pulse duration, CK, CK High or Low
Differential inputs active time (See notes 1 and 2)
Differential inputs inactive time (See notes 1 and 3)
Hold time
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
TYP
MAX
fmax
335
MHz
tPDM
1
CLK, CLK#
Q
1.41
1.75
ns
tPDMSS
2
CLK, CLK#
Q
1.95
ns
tphl
RESET#
Q
3
ns
Notes: 1. Includes 350ps test-load transmission-line delay
2. Guaranteed by design, not 100% tested in production.
SYMBOL
VDD = 1.8V ±0.1V
UNITS
From
(Input)
To
(Output)
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
MIN
MAX
dV/dt_r
1
4
V/ns
dV/dt_f
1
4
V/ns
dV/dt_
1
1V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
VDD = 1.8V ± 0.1V
UNIT
相关PDF资料 |
PDF描述 |
|---|---|
| ICSSSTUF32864YHLFT | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| ICSSSTUF32866EHT | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| ICSSSTUF32866EHLFT | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| ICSSSTVA16859CK-LF | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC56 |
| ICSSSTVA16859CK | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTV16857 | 制造商:ICS 制造商全称:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16857CG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16857YG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16857YL-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16859 | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
发布紧急采购，3分钟左右您将得到回复。