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参数资料
| 型号： | ICSSSTV16857YG-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封装： | 0.240 INCH, 0.50 MM PITCH, TSSOP-48 |
| 文件页数： | 5/8页 |
| 文件大小： | 114K |
| 代理商： | ICSSSTV16857YG-T |
5
ICSSSTV16857
Third party brands and names are the property of their respective owners.
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDD=2.5±0.2V
UNITS
MIN
TYP
MAX
fclock
Clock frequency
133
200
MHz
tPD
Clock to output time
1.1
2.4
2.8
ns
tRST
Reset to output time
3.1
5
ns
tSL
Output slew rate
1
1.5
4
V/ns
Setup time, fast slew rate
2, 4
Data before CK
D , CK#E
0.75
0.018
ns
tSU
Setup time, slow slew rate
3, 4
0.9
ns
Hold time, fast slew rate
2,4
Data after CK
D , CK#E
0.75
0.145
ns
Th
Hold time, slow slew rate
3, 4
0.9
ns
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate =1V/ns.
4 - CLK, CLK# signals input slew rates are =1V/ns.
3 - For data signal input slew rate =0.5V/ns and < 1V/ns.
Sw itching Characteristics
(over recom m ended operating free-air tem perature range, unles s otherwis e noted)
SYMBOL
From
To
VDD=2.5±0.2V
UNITS
(Input)
(Output)
MIN
TYP
MAX
fclock
133
200
MHz
tPD
CLK, CLK#
Q
1.1
2.4
2.8
ns
tph1
RESET#
Q
3.1
5
ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICSSSTV16857YL-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICSSSTV16859 | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859CG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859YG-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
| ICSSSTV16859YK | 制造商:ICS 制造商全称:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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