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参数资料
| 型号： | ICSSSTV32852YHLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114 |
| 封装： | BGA-114 |
| 文件页数： | 5/7页 |
| 文件大小： | 120K |
| 代理商： | ICSSSTV32852YHLFT |
5
ICSSSTV32852
0513F—05/13/03
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
fclock
Clock frequency
200
MHz
tPD
Clock to output time
1.9
2.7
ns
tRST
Reset to output time
4.5
ns
tSL
Output slew rate
1
4
V/ns
Setup time, fast slew rate
2, 4
0.50
ns
Setup time, slow slew rate
3, 4
0.70
ns
Hold time, fast slew rate
2, 4
0.30
ns
Hold time, slow slew rate
3, 4
0.50
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
VDD = 2.5V ±0.2V
UNITS
PARAMETERS
Data before CLK
↑, CLK#↓
Data after CLK
↑, CLK#↓
SYMBOL
tS
Th
Notes:
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
TYP
MAX
fmax
200
MHz
tPD
CLK, CLK#
Q
1.9
2.7
ns
tphl
RESET#
Q
4.5
ns
SYMBOL
VDD = 2.5V ±0.2V
UNITS
From
(Input)
To
(Output)
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