参数资料
型号: IDT49FCT806BTPY8
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: FCT SERIES, LOW SKEW CLOCK DRIVER, 0 TRUE OUTPUT(S), 5 INVERTED OUTPUT(S), PDSO20
封装: SSOP-20
文件页数: 6/7页
文件大小: 75K
代理商: IDT49FCT806BTPY8
6
MILITARYANDCOMMERCIALTEMPERATURERANGES
IDT49FCT806BT/CT
FAST CMOSBUFFER/CLOCKDRIVER
7V
VCC
Pulse
Generator
D.U.T.
500
500
RT
VIN
VOUT
50pF
CL
0V
VOH
tPLH
tPHL
VOL
tR
3V
1.5V
tF
2.0V
0.8V
1.5V
OUTPUT
INPUT
CONTROL
INPUT
tPLZ
0V
OUTPUT
NORMALLY
LOW
tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
OPEN
tPHZ
0V
VOL
VOH
0.3V
1.5V
tPZL
3.5V
3V
1.5V
0V
VOH
tPLH
tPHL
VOL
3V
1.5V
OUTPUT
INPUT
tSK(p) = tPHL - tPLH
0V
VOH
tPLH1
VOL
1.5V
OUTPUT 1
3V
1.5V
INPUT
VOH
tSK(o)
VOL
1.5V
tSK(o) = tPLH2 - tPLH1 or tPHL2 - tPHL1
OUTPUT 2
tPLH1
tSK(o)
tPLH2
tPHL2
0V
VOH
tPLH1
VOL
1.5V
PACKAGE 1
OUTPUT
3V
1.5V
INPUT
VOH
tSK(pp)
VOL
1.5V
tSK(p) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL1
tSK(pp)
tPLH2
tPHL2
PACKAGE 2
OUTPUT
Package Delay
TEST CIRCUITS AND WAVEFORMS
Pulse Skew - tSK(P)
Test Circuits for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test
Switch
Disable LOW
Closed
Enable LOW
Disable HIGH
GND
Enable HIGH
SWITCH POSITION
Enable and Disable Times
Output Skew
Part-to-Part Skew - tSK(PP)
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
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