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参数资料
| 型号： | IDT5T2010BBI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK |
| 中文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封装： | PLASTIC, BGA-144 |
| 文件页数： | 9/23页 |
| 文件大小： | 157K |
| 代理商： | IDT5T2010BBI |
9
INDUSTRIAL TEMPERATURE RANGE
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
DIFFERENT IAL INPUT AC T ES T CONDIT IONS FOR HS T L
Symbol
Parameter
V
DIF
Input Signal Swing
(1)
V
X
Differential Input Signal Crossing Point
(2)
V
THI
Input Timng Measurement Reference Level
(3)
t
R
, t
F
Input Signal Edge Rate
(4)
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the V
DIF
(AC)
specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the V
X
specification under
actual use conditions.
3. In all cases, input waveformtimng is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform
Value
1
750
Units
V
mV
V
V/ns
Crossing Point
1
DC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE FOR eHSTL
(1)
Symbol
Parameter
Test Conditions
Input Characteristics
I
IH
Input HIGH Current
V
DD
= 2.7V
I
IL
Input LOW Current
V
DD
= 2.7V
V
IK
Clamp Diode Voltage
V
DD
= 2.3V, I
IN
= -18mA
V
IN
DC Input Voltage
V
DIF
DC Differential Voltage
(2,8)
V
CM
DC Common Mode Input Voltage
(3,8)
V
IH
DC Input HIGH
(4,5,8)
V
IL
DC Input LOW
(4,6,8)
V
REF
Single-Ended Reference Voltage
(4,8)
Output Characteristics
V
OH
Output HIGH Voltage
I
OH
= -8mA
I
OH
= -100
μ
A
V
OL
Output LOW Voltage
I
OL
= 8mA
I
OL
= 100
μ
A
V
OX
FB/
FB
Output Crossing Point
Min.
Typ.
(7)
Max
Unit
V
I
= V
DDQ
/GND
V
I
= GND/V
DDQ
—
—
—
- 0.3
0.2
800
—
—
- 0.7
±5
±5
- 1.2
+3.6
—
1000
—
μ
A
V
V
V
900
mV
mV
mV
mV
V
REF
+ 100
—
—
V
REF
- 100
—
900
V
DDQ
- 0.4
V
DDQ
- 0.1
—
—
V
DDQ
/2 - 150
—
—
0.4
0.1
V
V
V
V
V
DDQ
/2
V
DDQ
/2 + 150
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. V
DIF
specifies the mnimuminput differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. V
CM
specifies the maximumallowable range of (V
TR
+ V
CP
) /2. Differential mode only.
4. For single-ended operation, in a differential mode,
REF
[1:0]
/V
REF
[1:0]
is tied to the DC voltage V
REF
[1:0]
.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at V
DD
= 2.5V, V
DDQ
= 1.8V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
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