参数资料
型号: IDT5V49EE901NLGI8
厂商: IDT, Integrated Device Technology Inc
文件页数: 7/36页
文件大小: 0K
描述: IC PLL CLK GEN 200MHZ 32VFQFN
产品培训模块: VersaClock™ III Programmable Clocks
特色产品: VersaClock III Timing Devices
标准包装: 2,500
系列: VersaClock™ III
类型: 时钟发生器,多路复用器
PLL: 带旁路
输入: LVCMOS,LVTTL,晶体
输出: HCSL,LVCMOS,LVDS,LVPECL,LVTTL
电路数: 1
比率 - 输入:输出: 2:9
差分 - 输入:输出: 无/是
频率 - 最大: 500MHz
除法器/乘法器: 是/是
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-VFQFPN 裸露焊盘(4x4)
包装: 带卷 (TR)
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
15
IDT5V49EE901
REV R 092412
Progrestore
EEPROM Interface
The IDT5V49EE901 can also store its configuration in an
internal EEPROM. The contents of the device's internal
programming registers can be saved to the EEPROM by
issuing a save instruction (ProgSave) and can be loaded
back to the internal programming registers by issuing a
restore instruction (ProgRestore).
To initiate a save or restore using I2C, only two bytes are
transferred. The Device Address is issued with the
read/write bit set to “0”, followed by the appropriate
command code. The save or restore instruction executes
after the STOP condition is issued by the Master, during
which time the IDT5V49EE901 will not generate
Acknowledge bits. The IDT5V49EE901 will acknowledge
the instructions after it has completed execution of them.
During that time, the I2C bus should be interpreted as busy
by all other users of the bus.
On power-up of the IDT5V49EE901, an automatic restore is
performed to load the EEPROM contents into the internal
programming registers. The IDT5V49EE901 will be ready to
accept a programming instruction once it acknowledges its
7-bit I2C address.
SAddress
R/W
ACK
Command Code
ACK
P
7-bits
0
1-bit
8-bits: xxxx xx10
1-bit
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