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参数资料
| 型号： | IDT7005L35PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 7/21页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 64KBIT 35NS 64TQFP |
| 标准包装： | 750 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 64K (8K x 8) |
| 速度： | 35ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7005L35PF8 |
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
5V
5V
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
GND to 3.0V
5ns Max.
1.5V
DATA OUT
BUSY
1250 ?
DATA OUT
1250 ?
Output Reference Levels
1.5V
INT
775 ?
30pF
775 ?
5pF*
Output Load
Figures 1 and 2
2738 tbl 12
Figure 1. AC Output Test Load
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (4)
2738 drw 06
Figure 2. Output Test Load
(For t LZ , t HZ , t WZ , t OW )
*Including scope and jig
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l, Ind
& Military
7005X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t RC
t AA
t ACE
t AOE
t OH
Read Cycle Time
Address Access Time
Chip Enable Access Time (3)
Output Enable Access Time
Output Hold from Address Change
15
____
____
____
3
____
15
15
10
____
17
____
____
____
3
____
17
17
10
____
20
____
____
____
3
____
20
20
12
____
25
____
____
____
3
____
25
25
13
____
ns
ns
ns
ns
ns
t LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
3
____
ns
t HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15
ns
t PU
Chip Enable to Power Up Time (2,5)
0
____
0
____
0
____
0
____
ns
t PD
Chip Disable to Power Down Time
(2,5)
____
15
____
17
____
20
____
25
ns
t SOP
t SAA
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
10
____
____
15
10
____
____
17
10
____
____
20
10
____
____
25
ns
ns
2738 tbl 13a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
IDT7005X70
Military
Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t RC
t AA
Read Cycle Time
Address Access Time
35
____
____
35
55
____
____
55
70
____
____
70
ns
ns
t ACE
Chip Enable Access Time
(3)
____
35
____
55
____
70
ns
t AOE
t OH
Output Enable Access Time
Output Hold from Address Change
____
3
20
____
____
3
30
____
____
3
35
____
ns
ns
t LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t HZ
t PU
Output High-Z Time (1,2)
Chip Enab le to Power Up Time (2,5)
____
0
15
____
____
0
25
____
____
0
30
____
ns
ns
t PD
Chip Disable to Power Down Time
(2,5)
____
35
____
50
____
50
ns
t SOP
t SAA
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
15
____
____
35
15
____
____
55
15
____
____
70
ns
ns
NOTES:
1. Transition is measured 0mV from Low or High impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not production tested.
3. To access RAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL .
4. 'X' in part number indicates power rating (S or L).
7
6.42
2738 tbl 13b
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT7005L35PFB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005L35XL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Dual-Port SRAM |
| IDT7005L35XLB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Dual-Port SRAM |
| IDT7005L45F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Dual-Port SRAM |
| IDT7005L45FB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Dual-Port SRAM |
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