参数资料
型号: IDT7005L55J
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: SRAM
英文描述: Dual, Ultra Low Cost, RRIO CMOS Amplifier; Package: MSOP; No of Pins: 8; Container: Tape & Reel
中文描述: 8K X 8 DUAL-PORT SRAM, 55 ns, PQCC68
封装: 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68
文件页数: 1/20页
文件大小: 189K
代理商: IDT7005L55J
2001 Integrated Device Technology, Inc.
NOVEMBER 2001
DSC 2738/14
1
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
WL
CEL
OEL
BUSYL
A12L
A0L
2738 drw 01
I/O0L- I/O7L
CEL
OEL
R/
WL
SEML
INTL
M/
S
BUSYR
I/O0R-I/O7R
A12R
A0R
SEMR
INTR
CER
OER
(2)
(1,2)
(2)
R/
WR
CER
OER
R/
WR
13
IDT7005S/L
HIGH-SPEED
8K x 8 DUAL-PORT
STATIC RAM
Features
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 35/55ns (max.)
– Commercial:15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7005L
Active: 700mW (typ.)
Standby: 1mW (typ.)
IDT7005 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/
S = H for BUSY output flag on Master,
M/
S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
thin quad flatpack
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
NOTES:
1. (MASTER):
BUSY is output; (SLAVE): BUSY is input.
2.
BUSY outputs and INT outputs are non-tri-stated push-pull.
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