参数资料
型号: IDT7005L55J
厂商: IDT, Integrated Device Technology Inc
文件页数: 8/21页
文件大小: 0K
描述: IC SRAM 64KBIT 55NS 68PLCC
标准包装: 18
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K (8K x 8)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24x24)
包装: 管件
其它名称: 7005L55J
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Waveform of Read Cycles
(5)
Military, Industrial and Commercial Temperature Ranges
t RC
ADDR
t AA (4)
CE
t ACE (4)
t AOE (4)
OE
R/ W
VALID DATA
DATA OUT
t LZ (1)
(4)
t OH
t HZ (2)
BUSY OUT
t BDD (3,4)
2738 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE .
2. Timing depends on which signal is de-asserted first CE or OE .
3. t BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t AOE , t ACE , t AA or t BDD .
5. SEM = V IH .
Timing of Power-Up Power-Down
CE
I CC
t PU
t PD
I SB
8
6.42
2738 drw 08
,
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