参数资料
型号: IDT7005S15J8
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/21页
文件大小: 0K
描述: IC SRAM 64KBIT 15NS 68PLCC
标准包装: 250
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K (8K x 8)
速度: 15ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24x24)
包装: 带卷 (TR)
其它名称: 7005S15J8
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (1) (M/ S = V IH )
ADDR "A"
and "B"
CE "A"
CE "B"
t APS (2)
t BAC
ADDRESSES MATCH
t BDC
BUSY "B"
2738 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (1) (M/ S = V IH )
t APS
ADDR "A"
(2)
ADDRESS "N"
ADDR "B"
t BAA
MATCHING ADDRESS "N"
t BDA
BUSY "B"
2738 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (1)
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l, Ind
& Military
7005X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
15
15
0
0
____
____
____
____
15
15
0
0
____
____
____
____
20
20
0
0
____
____
____
____
20
20
ns
ns
ns
ns
2738 tbl 16a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
7005X70
Military
Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
25
25
0
0
____
____
____
____
40
40
0
0
____
____
____
____
50
50
ns
ns
ns
ns
NOTES:
1. 'X' in part number indicates power rating (S or L).
14
6.42
2738 tbl 16b
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