参数资料
型号: IDT7005S17PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/21页
文件大小: 0K
描述: IC SRAM 64KBIT 17NS 64TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 64K (8K x 8)
速度: 17ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 7005S17PF8
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read with BUSY (2,5)
(M/ S = V IH ) (4)
t WC
ADDR "A"
MATCH
t WP
R/ W "A"
DATA IN "A"
t APS (1)
t DW
VALID
t DH
ADDR "B"
MATCH
BUSY "B"
t WDD
t BDA
t BDD
DATA OUT "B"
t DDD
NOTES:
1. To ensure that the earlier of the two ports wins. t APS is ignored for for M/S = V IL (slave).
2. CE L = CE R = V IL
3. OE = V IL for the reading port.
4. If M/ S = V IL (slave), then BUSY is an input ( BUSY " A" =V IH ), and BUSY " B" = "don't care", for this example.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
Timing Waveform of Write with BUSY
t WP
R/ W "A"
t WB (3)
(3)
VALID
2738 drw 13
BUSY "B"
R/ W "B"
(2)
t WH
(1)
2738 drw 14
NOTES:
1. t WH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B", blocking R/ W "B" , until BUSY "B" goes HIGH
3. t WB is only for the 'Slave' Version . .
13
6.42
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