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参数资料
| 型号： | IDT7005S55PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 15/21页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 64KBIT 55NS 64TQFP |
| 标准包装： | 750 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 64K (8K x 8) |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7005S55PF8 |
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Waveform of Interrupt Timing (1)
t WC
Military, Industrial and Commercial Temperature Ranges
ADDR "A"
t AS (3)
INTERRUPT SET ADDRESS (2)
t WR (4)
CE "A"
R/ W "A"
t INS (3)
INT "B"
2738 drw 17
t RC
ADDR "B"
INTERRUPT CLEAR ADDRESS (2)
t AS (3)
CE "B"
OE "B"
t INR (3)
INT "B"
2738 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal ( CE or R/ W ) asserted last.
4. Timing depends on which enable signal ( CE or R/ W ) is de-asserted first.
Truth Table III — Interrupt Flag (1,4)
Left Port
Right Port
L
H
L
H
R/ W L
L
X
X
X
CE L
L
X
X
L
OE L
X
X
X
L
A 12L -A 0L
1FFF
X
X
1FFE
INT L
X
X
(3)
(2)
R/ W R
X
X
L
X
CE R
X
L
L
X
OE R
X
L
X
X
A 12R -A 0R
X
1FFF
1FFE
X
INT R
(2)
(3)
X
X
Function
Set Right INT R Flag
Reset Right INT R Flag
Set Left INT L Flag
Reset Left INT L Flag
2738 tbl 17
NOTES:
1. Assumes BUSY L = BUSY R = V IH .
2. If BUSY L = V IL , then no change.
3. If BUSY R = V IL , then no change.
4. INT R and INT L must be initialized at power-up.
15
6.42
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相关代理商/技术参数 |
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|---|---|
| IDT7005S55PFB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005S55PFI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Dual-Port SRAM |
| IDT7005S55XL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Dual-Port SRAM |
| IDT7005S55XLB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 Dual-Port SRAM |
| IDT7005S70F | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
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