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参数资料
| 型号： | IDT7006L45J8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 128KBIT 45NS 68PLCC |
| 标准包装： | 250 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 128K (16K x 8) |
| 速度： | 45ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 68-LCC（J 形引线） |
| 供应商设备封装： | 68-PLCC（24x24） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7006L45J8 |
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side (1)
t SAA
t OH
A 0 -A 2
VALID ADDRESS
VALID ADDRESS
SEM
DATA 0
t AW
t EW
t WR
t DW
DATA IN VALID
t SOP
t ACE
DATA OUT
VALID
R/ W
t AS
t WP
t DH
OE
Write Cycle
t SWRD
t SOP
Read Cycle
t AOE
2739 drw 11
NOTE:
1. CE = V IH for the duration of the above timing (both write and read cycle).
Timing Waveform of Semaphore Write Contention (1,3,4)
A 0"A" -A 2"A"
MATCH
(2)
SIDE
(2)
SIDE
“A”
“B”
R/ W "A"
SEM "A"
A 0"B" -A 2"B"
R/ W "B"
SEM "B"
MATCH
t SPS
2739 drw 12
NOTES:
1. D OR = D OL = V IL , CE R = CE L = V IH , Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/ W "A" or SEM "A" going HIGH to R/ W "B" or SEM "B" going HIGH.
4. If t SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
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