参数资料
型号: IDT7006L55J
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/20页
文件大小: 0K
描述: IC SRAM 128KBIT 55NS 68PLCC
标准包装: 18
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 128K (16K x 8)
速度: 55ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24x24)
包装: 管件
其它名称: 7006L55J
HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
IDT7006S/L
True Dual-Ported memory cells which allow simultaneous
High-speed access
Features
reads of the same memory location
– Military: 20/25/35/55/70ns (max.)
M/ S = H for BUSY output flag on Master,
M/ S = L for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7006L
Active: 700mW (typ.)
Standby: 1mW (typ.)
IDT7006 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
one device
Functional Block Diagram
BUSY L
OE L
CE L
R/ W L
I/O 0L - I/O 7L
(1,2)
I/O
Control
I/O
Control
OE R
CE R
R/ W R
I/O 0R -I/O 7R
BUSY R (1,2)
A 13L
A 0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A 13R
A 0R
14
14
INT L
INT R
SEM L
(2)
CE L
OE L
R/ W L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
CE R
OE R
R/ W R
SEM R
(2)
2739 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
?2008 Integrated Device Technology, Inc.
1
OCTOBER 2008
DSC- 2739/16
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