参数资料
型号: IDT7008S15PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/19页
文件大小: 0K
描述: IC SRAM 512KBIT 15NS 100TQFP
标准包装: 750
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 512K (64K x 8)
速度: 15ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 7008S15PF8
HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM
IDT7008S/L
True Dual-Ported memory cells which allow simultaneous
Features
reads of the same memory location
IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
High-speed access
than one device
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/55ns (max.)
– Military: 25/35/55ns (max.)
M/ S = V IH for BUSY output flag on Master,
M/ S = V IL for BUSY input on Slave
Interrupt Flag
Low-power operation
– IDT7008S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7008L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/ W L
CE 0L
CE 1L
OE L
R/ W R
CE 0R
CE 1R
OE R
BUSY L
BUSY R
I/O 0-7L
(1,2)
I/O
Control
I/O
Control
I/O 0-7R
(1,2)
A 15L
A 0L
Address
Decoder
64Kx8
MEMORY
ARRAY
7008
Address
Decoder
A 15R
A 0R
16
16
INT L
M/ S
INT R
SEM L
(2)
CE 0L
CE 1L
OE L
R/ W L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
(1)
CE 0R
CE 1R
OE R
R/ W R
SEM R
(2)
3198 drw 01
NOTES:
1. BUSY is an input as a Slave (M/ S = V IL ) and an output when it is a Master (M/ S = V IH ).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
?2008 Integrated Device Technology, Inc.
1
OCTOBER 2008
DSC 3198/9
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