参数资料
型号: IDT7008S35G
厂商: IDT, Integrated Device Technology Inc
文件页数: 8/19页
文件大小: 0K
描述: IC SRAM 512KBIT 35NS 84PGA
标准包装: 3
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 512K (64K x 8)
速度: 35ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 84-BPGA
供应商设备封装: 84-PGA(27.94x27.94)
包装: 托盘
其它名称: 7008S35G
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
5V
5V
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
GND to 3.0V
5ns Max.
1.5V
DATA OUT
BUSY
893 ?
DATA OUT
893 ?
Output Reference Levels
1.5V
INT
347 ?
30pF
347 ?
5pF*
Output Load
Figures 1 and 2
3198 tbl 11
3198 drw 05
Figure 1. AC Output Test Load
3198 drw 06
Figure 2. Output Test Load
(for t LZ , t HZ , t WZ , t OW )
* Including scope and jig.
Waveform of Read Cycles (5)
t RC
ADDR
CE (6)
(4)
t AA
(4)
t ACE
OE
R/ W
t AOE
(4)
DATA OUT
BUSY OUT
t LZ
(1)
(4)
VALID DATA
t OH
(2)
t HZ
Timing of Power-Up Power-Down
(6)
CE
t BDD
(3,4)
3198 drw 07
I CC
t PU
t PD
I SB
3198 drw 08
,
NOTES:
1. Timing depends on which signal is asserted last, OE or CE .
2. Timing depends on which signal is de-asserted first CE or OE .
3. t BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t AOE , t ACE , t AA or t BDD .
5. SEM = V IH .
6. Refer to Chip Enable Truth Table.
8
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