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| 型号： | IDT7008S35J |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/19页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 512KBIT 35NS 84PLCC |
| 标准包装： | 9 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 512K (64K x 8) |
| 速度： | 35ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 84-LCC（J 形引线） |
| 供应商设备封装： | 84-PLCC（29.21x29.21） |
| 包装： | 管件 |
| 其它名称： | 7008S35J |
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (1,5,8)
t WC
ADDRESS
CE or SEM
OE
(9,10)
t AW
t HZ
(7)
t AS (6)
t WP (2)
t WR
(3)
R/ W
t WZ
(7)
t OW
DATA OUT
(4)
t DW
t DH
(4)
DATA IN
3198 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,5)
t WC
ADDRESS
t AW
CE or SEM (9,10)
t WR
t AS
(6)
t EW (2)
(3)
R/ W
t DW
t DH
DATA IN
3198 drw 10
NOTES:
1. R/ W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a LOW CE and a LOW R/ W for memory array writing cycle.
3. t WR is measured from the earlier of CE or R/ W (or SEM or R/ W ) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/ W .
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t DW . If OE is HIGH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified t WP .
9. To access RAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . t EW must be met for either condition.
10. Refer to Chip Enable Truth Table.
10
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| IDT7008S35J8 | 功能描述:IC SRAM 512KBIT 35NS 84PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT7008S35JB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM |
| IDT7008S35JI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM |
| IDT7008S35PF | 功能描述:IC SRAM 512KBIT 35NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT7008S35PF8 | 功能描述:IC SRAM 512KBIT 35NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
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