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参数资料
| 型号： | IDT7015L35PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 72KBIT 35NS 80TQFP |
| 标准包装： | 750 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 72K（8K x 9） |
| 速度： | 35ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7015L35PF8 |
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Waveform of Read Cycles
(5)
Military, Industrial and Commercial Temperature Ranges
t AA
t RC
ADDR
(4)
CE
OE
R/ W
t ACE
t AOE
(4)
(4)
t BDD
DATA OUT
BUSY OUT
t LZ
(1)
(4)
VALID DATA
(3,4)
t OH
(2)
t HZ
2954 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE .
2. Timing depends on which signal is de-asserted first, CE or OE .
3. t BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t AOE , t ACE , t AA or t BDD .
5. SEM = V IH .
Timing of Power-Up / Power-Down
CE
I CC
t PU
t PD
I SB
50%
50%
,
2954 drw 08
8
6.42
相关PDF资料 |
PDF描述 |
|---|---|
| IDT7015L25PF8 | IC SRAM 72KBIT 25NS 80TQFP |
| IDT7015L20PF8 | IC SRAM 72KBIT 20NS 80TQFP |
| IDT7005L35PF8 | IC SRAM 64KBIT 35NS 64TQFP |
| IDT7005L25PF8 | IC SRAM 64KBIT 25NS 64TQFP |
| IDT7005L20PF8 | IC SRAM 64KBIT 20NS 64TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT7015L35PFB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015L35PFI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015S | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015S_06 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015S12G | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
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