- 您现在的位置：买卖IC网 > PDF目录4046 > IDT7016L15PF8 (IDT, Integrated Device Technology Inc)IC SRAM 144KBIT 15NS 80TQFP PDF资料下载
参数资料
| 型号： | IDT7016L15PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 144KBIT 15NS 80TQFP |
| 标准包装： | 750 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 144K（16K x 9） |
| 速度： | 15ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7016L15PF8 |
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (1,5,8)
t WC
ADDRESS
t HZ (7)
OE
t AW
CE or SEM
(9)
t AS (6)
t WP (2)
t WR
(3)
R/ W
DATA OUT
t LZ
t WZ (7)
(4)
t DW
t OW
t DH
(4)
DATA IN
3190 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,5)
t WC
ADDRESS
t AW
CE or SEM
(9)
(6)
t AS
t EW (2)
t WR
(3)
R/ W
t DW
t DH
DATA IN
3190 drw 10
NOTES:
1. R/ W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a LOW CE and a LOW R/ W for memory array writing cycle.
3. t WR is measured from the earlier of CE or R/ W (or SEM or R/ W ) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/ W .
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t DW . If OE is HIGH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified t WP .
9. To access RAM, CE = V IL and SEM = V IH . To access Semaphore, CE = V IH and SEM = V IL . t EW must be met for either condition.
10
6.42
相关PDF资料 |
PDF描述 |
|---|---|
| IDT7006L20PFI8 | IC SRAM 128KBIT 20NS 64TQFP |
| IDT7006L20PFGI8 | IC SRAM 128KBIT 20NS 64TQFP |
| XC4044XL-1HQ160I | IC FPGA I-TEMP 3.3V 1SPD 160HQFP |
| XC4044XL-1HQ160C | IC FPGA C-TEMP 3.3V 1SPD 160HQFP |
| XC4044XL-1BG432I | IC FPGA I-TEMP 3.3V 1SPD 432MBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT7016L15PFB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM |
| IDT7016L15PFG | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L15PFGB | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L15PFGI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L17J | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x9 Dual-Port SRAM |
发布紧急采购，3分钟左右您将得到回复。