参数资料
型号: IDT7016L25J
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/20页
文件大小: 0K
描述: IC SRAM 144KBIT 25NS 68PLCC
标准包装: 18
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 144K(16K x 9)
速度: 25ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24x24)
包装: 管件
其它名称: 7016L25J
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read with BUSY
(2,4,5)
t WC
(M/ S = V IH )
ADDR "A"
MATCH
t WP
R/ W "A"
DATA IN "A"
t APS (1)
t DW
VALID
t DH
ADDR "B"
MATCH
BUSY "B"
t WDD
DATA OUT "B"
t DDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. t APS is ignored for M/ S =V IL .
2. CE L = CE R = V IL .
3. OE = V IL for the reading port.
4. If M/ S =V IL (SLAVE), BUSY is an input. Then for this example BUSY “A” = V IH and BUSY “B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
Timing Waveform of Write with BUSY (3)
t WP
R/ W "A"
t WB
t BDA
t BDD
VALID
3190 drw 13
BUSY "B"
R/ W "B"
(2)
t WH
(1)
,
3190 drw 14
NOTES:
1. t WH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/ W "B" , until BUSY "B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
13
6.42
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